(1) Field of the Invention
The present invention relates to the manufacture of integrated circuits in general, and in particular, to a method of controlling corrosion of copper lines through management of stresses in barrier metals formed to bar diffusion of copper.
(2) Description of the Related Art
In general, corrosion of metal lines in semiconductor devices can be caused by many factors, including the transport of moisture and other contaminants and subsequent reaction of these with the metal lines. The moisture and contaminants may either exist in a semiconductor package material itself, or may arrive through cracks in the package. Or, there may be leaching of certain species such as phosphorus form phosphorous-doped SiO.sub.2 intermetal of passivation dielectric layers, followed by reaction of the phosphorus with absorbed moisture to form phosphoric acid, which then attacks aluminum, when aluminum lines are used. Or, residual process chlorine may react with moisture to form hydrochloric acid, which then attacks metal lines. In the case of copper lines, which are more and more coming into use in semiconductor devices, the corrosion problem is exacerbated by the tendency of the copper to diffuse into surrounding materials, such as polyimides, during high temperature processing of the polyimide. Copper then combines with oxygen in the polyimide, which in turn causes severe corrosion. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the metal line. A copper diffusion barrier is therefore often required.
The use of copper (Cu) metal in interconnection metallurgy systems has long been considered as an alternative metallization material to aluminum (Al) and Al alloys due to its low resistivity and ability to reliably carry high current densities. However, its use has presented many problems, such as the possibility of diffusion into the semiconductor substrate, the low adhesive strength of Cu to various insulating layers and the difficulties inherent in masking and etching the blanket Cu layer into intricate circuit structures. In particular, diffusivity of copper and the attendant corrosion problems can cause serious reliability problems in integrated circuits. In its simplest form, using damascene process for example, --which is described in more detail below--a trench or groove of desired shape, depth and length is formed in an insulator, and then filled with copper, to form a copper line, or interconnect. Unless the inside walls of the trench are lined properly, Cu will corrode with the attendant problems of peeling, delamination, and so on. To prevent these problems, it is common first to deposit a barrier metal inside the trench prior to depositing copper. However, the process stresses that are formed within the barrier can cause cracks and voids, which in turn harbor moisture, thereby promoting unwanted corrosion. It is disclosed later in the embodiments of the present invention a method of subjecting the barrier metal to high or low temperature deposition followed by a specific step of cooling down or thermal annealing, in order to manageably relieve the stresses for the purposes of resolving metal corrosions.
Damascene process provides a method of forming conductor lines by depositing metal into preformed channels in insulating materials. The channels are formed by etching into the insulating material, and the depositing of the metal is normally accomplished by chemical vapor deposition (CVD). The damascene process has the advantage of being simple in comparison with the conventional methods of depositing a layer of metal over an insulating material, and then substractively etching the metal to form the desired metal line patterns. Damascene process is especially useful in forming not only a channel for the line, but also for forming simultaneously the underlying hole that connects to the metal layer below in a semiconductor substrate. The resulting dual-damascene interconnect is formed with one step by filling both the channel and the hole with metal.
However, filling a dual damascene structure with metal can pose problems, especially when the dimensions of the channel and the hole are small. As will be appreciated by those skilled in the art, advances in the present day ultra scale integrated (ULSI) technology demand features smaller than 0.25 micrometers (.mu.m), and the correspondingly ultra small interconnects. One of the problems is illustrated in a prior art dual damascene shown in FIGS. 1a-1c. In FIG. 1a, substrate (10) is provided having metal layer (20) formed thereon. Insulating layer (30) is formed over the metal layer. A dual damascene structure having a channel or line trench (50) and a via or a contact hole (40) is etched into insulating layer (30), in a manner to be described more in detail later. Metal is next deposited into the damascene structure. However, in the case of copper as the metal, the inside walls of the composite dual damascene structure comprising the trench and the hole opening are first lined with barrier layer (60). It is the experience of the present manufacturing line that without proper management of process stresses, the barrier metal cracks and breaks-off at the edge of the damascene structure --reference numeral (95) in FIG. 1c--during the chemical-mechanical polishing (CMP) of the excess metal over the damascene interconnect. This is in addition to the stress induced internal stress cracks (80) within the barrier metal and extending into the bulk copper (70), as shown by reference numeral (90) in FIG. 1b. The damage caused through the interaction of highly stressed barrier metal and the abrasive action of the CMP pad, namely (90) in FIG. 1c, makes the so-formed damascene metal line susceptible to capturing moisture and other process contaminants, thus subjecting the copper metal to corrosion.
In one approach for a dual damascene process, two insulator layers (120) and (130) are formed on a substrate (100) with an intervening etch-stop layer (125), as shown in FIG. 2a. Substrate (100) is provided with metal layer (110) and a barrier layer (115). Using conventional photolithographic methods and photoresist (160), the upper insulator layer (130) is first etched, or patterned, with hole (170), as shown in FIG. 2a. The hole pattern is also formed into etch-stop layer (125). Then, the first photoresist mask is replaced with second mask (140) having a trench pattern, and the upper layer is etched to form trench (150) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (120), as shown in FIG. 2b. It will be noted that the etch-stop layer stops the etching of the trench into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (180), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in FIG. 2c.
Or, the order in which the trench and the hole are formed can be reversed (not shown). That is, using a first photoresist mask, a desired trench or trench pattern is first etched into the upper insulator material (130). The etching stops on etch-stop layer (125). Next, a second photoresist layer is formed over the substrate, thus filling the trench opening (150), and patterned with hole opening (170) The hole pattern is then etched into the lower insulator layer (120) and photoresist removed, thus forming the dual damascene structure shown in FIG. 2c. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers. However, as it will be obvious to those skilled in the art, contacts or vias with cracks, or other types of damage exposed to the manufacturing line will experience corrosion. It is important, therefore, that copper interconnect is provided with a barrier lining, and that it is stress-free to the extent that it will not be damaged during CMP. A conventional barrier lining (185), formed prior to the deposition of copper metal (180), is shown in FIG. 2c where stress induced internal cracks (190) and surface damage (195) caused by CMP interaction are also shown.
In prior art, methods have been devised to improve metal barriers. In U.S. Pat. No. 6,030,896, Brown teaches forming a self-aligned copper interconnect architecture with enhance copper diffusion barrier. A via is formed in a semiconductor device using a self-aligned copper-based pillar to connect upper and lower copper interconnect layers separated by a dielectric. The lower interconnect layer is formed on an underlying layer. The copper-based via pillar is formed on the lower interconnect layer. The upper interconnect layer is formed to make electrical contact to the exposed upper surface of the via [pillar. Conductive diffusion barrier material is formed on vertical sidewalls of the lower interconnect layer.
In another U.S. Pat. No. 6,001,730, Frakas, et al., disclose a method for forming a copper interconnect on an integrated circuit using tantalum based barrier layers. A tantalum layer is formed within an opening in a dielectric layer. A copper layer is formed over the barrier layer. a first CMP process is used to polish the copper to expose portions of the barrier. a second CMP process which different from the first CMP process is then used to polish exposed portions of the layer faster than the dielectric layer or the copper layer. After this two-step CMP process, a copper interconnect having a tantalum based barrier is formed across the integrated circuit substrate.
In U.S. Pat. No. 6,025,259, Yu, et al., teach a method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having dimension coinciding with a width dimension of the first trench. The two layers of interlayer dielectric and the first, second and third etch stop layers are etched to form a second dual demesne structure having a second via and a second trench having the same dimensions as the first dual damascene structure.